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 HD74HC137
3-to-8-line Decoder/Demultiplexer with Address Latch
REJ03D0569-0200 (Previous ADE-205-443) Rev.2.00 Oct 11, 2005
Description
The HD74HC137 implements a three-to-eight line decoder with latches on the three address inputs. When GL goes from low to high, the address present at the select inputs (A, B and C) is stored in the latches. As long as GL remains high no address changes will be recognized. Output enable controls, G1 and G2, control the state of the outputs independently of the select or latch-enable inputs. All of the outputs are high unless G1 is high and G2 is low. The HD74HC137 is ideally suited for the implementation of glitchfree decoders in stored-address applications in bus oriented systems.
Features
* * * * * * High Speed Operation: tpd (A, B, C to Y) = 16.5 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 V to 6 V Low Input Current: 1 A max Low Quiescent Supply Current: ICC (static) = 4 A max (Ta = 25C) Ordering Information
Part Name HD74HC137P HD74HC137FPEL HD74HC137RPEL Package Type DILP-16 pin SOP-16 pin (JEITA) SOP-16 pin (JEDEC) Package Code (Previous Code) PRDP0016AE-B (DP-16FV) PRSP0016DH-B (FP-16DAV) PRSP0016DG-A (FP-16DNV) Package Abbreviation P FP RP -- EL (2,000 pcs/reel) EL (2,500 pcs/reel) Taping Abbreviation (Quantity)
Note: Please consult the sales office for the above package availability.
Rev.2.00, Oct 11, 2005 page 1 of 9
HD74HC137
Function Table
Inputs GL X X L L L L L L L L H H: L: X: Enable G1 X L H H H H H H H H H High level Low level Irrelevant G2 H X L L L L L L L L L C X X L L L L H H H H X Select B X X L L H H L L H H X Outputs A X X L H L H L H L H X Y0 H H L H H H H H H H Y1 Y2 Y3 Y4 Y5 Y6 Y7 H H H H H H H H H L H H H H H H H H H H H H H H H H H H L H H H H H H L H H H H H H L H H H H H H L H H H H H H L H H H H H H L H H H H H H Output Corresponding to stored address L; all Others. H
Pin Arrangement
A1 B2 C3 GL 4 G2 5 G1 6 Y7 7 GND 8 B C GL G2 G1 Y7 Y6 A Y0 Y1 Y2 Y3 Y4 Y5
16 VCC 15 Y0 14 Y1 13 Y2 12 Y3 11 Y4 10 Y5 9 Y6
(Top view)
Rev.2.00, Oct 11, 2005 page 2 of 9
HD74HC137
Logic Diagram
A
Y0
Y1
B
Y2
Y3
C
Y4
Y5 GL Y6
G2 G1
Y7
Absolute Maximum Ratings
Item Supply voltage range Input voltage Output voltage Output current DC current drain per VCC, GND DC input diode current DC output diode current Power dissipation per package Storage temperature Symbol VCC VIN VOUT IOUT ICC, IGND IIK IOK PT Tstg Rating -0.5 to +7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 25 50 20 20 500 -65 to +150 Unit V V V mA mA mA mA mW C
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time.
Rev.2.00, Oct 11, 2005 page 3 of 9
HD74HC137
Recommended Operating Conditions
Item Supply voltage Input / Output voltage Operating temperature Input rise / fall time Note:
*1
Symbol VCC VIN, VOUT Ta tr , tf
Ratings 2 to 6 0 to VCC -40 to 85 0 to 1000 0 to 500 0 to 400
Unit V V C
Conditions
VCC = 2.0 V ns VCC = 4.5 V VCC = 6.0 V
1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics.
Electrical Characteristics
Ta = 25C Item Input voltage Symbol VCC (V) VIH 2.0 4.5 6.0 VIL 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 VOL 2.0 4.5 6.0 4.5 Input current Quiescent supply current Iin ICC 6.0 6.0 6.0 Min 1.5 3.15 4.2 -- -- -- 1.9 4.4 5.9 4.18 5.68 -- -- -- -- -- -- -- Typ -- -- -- -- -- -- 2.0 4.5 6.0 -- -- 0.0 0.0 0.0 -- -- -- -- Max -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.26 0.26 0.1 4.0 Ta = -40 to+85C Min 1.5 3.15 4.2 -- -- -- 1.9 4.4 5.9 4.13 5.63 -- -- -- -- -- -- -- Max -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.33 0.33 1.0 40 V IOH = -4 mA IOH = -5.2 mA Vin = VIH or VIL IOL = 20 A V Unit V Test Conditions
Output voltage
VOH
V
Vin = VIH or VIL IOH = -20 A
IOL = 4 mA IOL = 5.2 mA A Vin = VCC or GND A Vin = VCC or GND, Iout = 0 A
Rev.2.00, Oct 11, 2005 page 4 of 9
HD74HC137
Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = 25C Item Propagation delay time Symbol VCC (V) tPLH 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 -- Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 80 16 14 100 20 17 50 10 9 -- -- -- -- Typ -- 16 -- -- 17 -- -- 13 -- -- 14 -- -- 14 -- -- 14 -- -- 17 -- -- 18 -- -- 7 -- -- 3 -- -- -3 -- -- 5 -- 5 Max 170 34 29 240 48 41 130 26 22 195 39 33 150 30 26 195 39 33 175 35 30 250 50 43 -- -- -- -- -- -- -- -- -- 75 15 13 10 Ta = -40 to +85C Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 100 20 17 125 25 21 65 13 11 -- -- -- -- Max 215 43 37 305 60 51 165 33 28 245 49 42 190 38 33 245 49 42 220 44 37 315 63 54 -- -- -- -- -- -- -- -- -- 90 19 16 10 Unit ns Test Conditions A, B or C to Y
tPHL
ns
tPLH
ns
G2 to Y
tPHL
ns
tPLH
ns
G1 to Y
tPHl
ns
tPLH
ns
GL to Y
tPHL
ns
Pulse width
tw
ns
Setup time
tsu
ns
A, B, C inputs
Hold time
th
ns
A, B, C inputs
Output rise/fall time Input capacitance
tTLH, tTHL
ns
Cin
pF
Test Circuit
Measurement point
CL*
Note: CL includes the probe and fig capacitance.
Rev.2.00, Oct 11, 2005 page 5 of 9
HD74HC137 Waveforms
* Waveform - 1
6ns 6ns 90% 10% 90% 50% 10%
Input A,B,C
90% 10%
90% 50% 10%
VCC 0V
tW tPLH Output Y
10% 90% 50%
tW tPHL
90% 50% 10%
VOH VOL
tTLH
tTHL
Notes: 1. Input waveform: PRR 1 MHz, Zo = 50 , tr 6 ns, tf 6 ns 2. The output are measured one at a time with one transition per measurement.
* Waveform - 2
6ns 6ns 90% 50% 10% 10%
G2
90% 50%
VCC 0V
tPHL
90%
tPLH
50% 10% 90% 50% 10%
VOH VOL
Output Y
tTHL
tTLH
Notes: 1. Input waveform: PRR 1 MHz, Zo = 50 , tr 6 ns, tf 6 ns 2. The output are measured one at a time with one transition per measurement.
* Waveform - 3
6ns 6ns 90% 50% 10% 90% 50% 10%
G1
VCC 0V
tPHL
90%
tPLH
50% 10% 90% 50% 10%
VOH VOL
Output Y
tTHL
tTLH
Notes: 1. Input waveform: PRR 1 MHz, Zo = 50 , tr 6 ns, tf 6 ns 2. The output are measured one at a time with one transition per measurement.
Rev.2.00, Oct 11, 2005 page 6 of 9
HD74HC137
* Waveform - 4
6ns 90% 50% 10% 10% 6ns 90% 50%
GL
VCC
50%
tW tPLH Output Y
10% 90% 50%
0V tPHL
90% 50% 10%
VOH VOL
tTLH
tTHL
Notes: 1. Input waveform: PRR 1 MHz, Zo = 50 , tr 6 ns, tf 6 ns 2. The output are measured one at a time with one transition per measurement.
* Waveform - 5
tW Input A,B,C VCC
50% 50%
0V tsu th VCC GL
50%
0V
Notes: 1. Input waveform: PRR 1 MHz, Zo = 50 , tr 6 ns, tf 6 ns 2. The output are measured one at a time with one transition per measurement.
Rev.2.00, Oct 11, 2005 page 7 of 9
HD74HC137
Package Dimensions
JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g
D
16
9
1 0.89 b3
8
Z
E
A1
A
Reference Symbol
Dimension in Millimeters Min Nom 7.62 19.2 6.3 20.32 7.4 5.06 0.51 0.40 0.48 1.30 0.19 0 2.29 2.54 0.25 0.31 15 2.79 1.12 2.54 0.56 Max
e D E
1
L
A A1
e
bp
e1
b c b c
p 3
e Z ( Ni/Pd/Au plating ) L
JEITA Package Code P-SOP16-3.95x9.9-1.27
RENESAS Code PRSP0016DG-A
Previous Code FP-16DNV
MASS[Typ.] 0.15g
*1
D 9
F
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
Index mark
*2
E
HE
c
Reference Symbol
Dimension in Millimeters Min Nom 9.90 3.95 Max 10.30
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2
8 bp x M L1
A1 A bp b1 c c
1
0.10
0.14
0.25 1.75
0.34
0.40
0.46
0.15
0.20
0.25
HE
0 5.80 6.10 1.27
8 6.20
A
A1
L y
e x y
0.25 0.15 0.635 0.40
1
Detail F
Z L L 0.60 1.08
1.27
Rev.2.00, Oct 11, 2005 page 8 of 9
HD74HC137
JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B Previous Code FP-16DAV MASS[Typ.] 0.24g
*1
D F 9
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
E
Index mark
Reference Symbol
*2
c
Dimension in Millimeters Min Nom 10.06 5.50 Max 10.5
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2
8 bp x M L1
A1 A bp b1 c
0.00
0.10
0.20 2.20
0.34
0.40
0.46
0.15
1
0.20
0.25
A
c
HE
0 7.50 7.80 1.27
8 8.00
A1
y L
e x y
0.12 0.15 0.80 0.50
1
Detail F
Z L L 0.70 1.15
0.90
Rev.2.00, Oct 11, 2005 page 9 of 9
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
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